In a semiconductor storage device in which bit lines of a memory cell array are constituted by impurity conduction regions provided in the substrate surface, there are no separation areas between the transistors that separates memory cells and therefore the memory cells can be made small in size. This is suitable for increasing storage capacity. However, since the bit lines are composed by the impurity conduction regions provided in the silicon substrate surface, the device cannot be adapted to high-speed operation owing to the resistance and stray capacitance, etc., of the bit lines. As a result of the increase in storage capacity, the bit lines become greater in length and high-speed operation is difficult to achieve. Another problem is that an increase in the length of the bit lines results in reduced write voltage applied to the memory cell, wherein the decline in write voltage is ascribable to the resistance of the bit lines. A semiconductor device for solving these problems has been proposed by the present applicant in the specification of Japanese Patent Application No. 2001-394216.
As one example of background art relating to the present invention, consider a rewritable non-volatile semiconductor device having an ONO(Oxide-Nitride-Oxide) 3-layer stack as a gate dielectric structure. This will be described with reference to FIG. 4.
As shown in FIG. 4, an ONO layer 122 provided on a channel between N+ diffusion regions 124 of a P-type silicon substrate 121 is obtained by forming first a film of silicon oxide, then forming a film of silicon nitride which functions as an electron trapping layer, on the silicon oxide film, and then forming a film of silicon oxide on the silicon nitride film. An electrically conductive gate electrode 125 is formed on the ONO layer 122. FIG. 4 schematically illustrates an arrangement in which two bits are stored in one memory cell.
Polysilicon used as the gate electrode has a comparatively high specific resistance. Accordingly, it has been contemplated to lower the gate film resistance by building up a silicide of a high-melting-point metal or semiprecious metal such as MoSi2, Wsi2, TiSi2, CoSi2 or the like, on the gate polysilicon.
Furthermore, in order to suppress gate resistance and source-drain resistance ascribable to finer patterns, a Salicide(Self-aligned silicide) structure in which source and drain are silicidated together with a gate electrode by a single process has become important as a technique for reducing the resistance of the gate electrode as well as the source-drain resistance.
In a case where this Salicide technique is applied to a non-volatile semiconductor storage device in which bit lines are constructed by impurity conduction regions (N+ diffusion regions) provided in a silicon substrate and which has an ONO layer as the gate dielectric layer, on the surface of the silicon substrate between the impurity conduction regions besides the regions where the gate electrodes are formed reacts with a high-melting-point metal together with the gate polysilicon. As a result, silicidation takes place, element isolation afforded by the PN junction ceases to function and the N+ diffusion regions are short-circuited. This problem will be described later in greater detail.